LIBRARY ieee;
library UNISIM;
USE ieee.std_logic_1164.ALL;
use UNISIM.Vcomponents.all;

ENTITY MICROP_T1 IS
END MICROP_T1;
 
ARCHITECTURE behavior OF MICROP_T1 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT THE_MAIN_THING
    PORT(
		clk : in STD_LOGIC;
		
		-- UART input
		in1 : in STD_LOGIC_VECTOR(31 downto 0);
		in2 : in STD_LOGIC_VECTOR(31 downto 0);
		
		-- UART output
		res1 : out STD_LOGIC_VECTOR(31 downto 0);
		res2 : out STD_LOGIC_VECTOR(31 downto 0);
		
		-- Debuggin output for signals
		wb_stage_val : out STD_LOGIC_VECTOR(31 downto 0);
		wb_stage_dest : out STD_LOGIC_VECTOR(4 downto 0);
		
		exec_to_dm_alu : out STD_LOGIC_VECTOR(31 downto 0);
		branch_and : out STD_LOGIC;
		
		debug_stall_if : out STD_LOGIC;
		debug_pc_if : out STD_LOGIC_VECTOR(31 downto 0);
		
		debug_asshole : out STD_LOGIC_VECTOR(4 downto 0)
	  );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
	
	signal in1 : STD_LOGIC_VECTOR(31 downto 0);
	signal in2 : STD_LOGIC_VECTOR(31 downto 0);

 	--Outputs
   signal res1 : std_logic_vector(31 downto 0);
   signal res2 : std_logic_vector(31 downto 0);
	signal wb_stage_val : STD_LOGIC_VECTOR(31 downto 0);
	signal wb_stage_dest : STD_LOGIC_VECTOR(4 downto 0);

	signal exec_to_dm_alu : STD_LOGIC_VECTOR(31 downto 0);
	signal branch_and : STD_LOGIC;
	
	signal debug_stall_if : STD_LOGIC;
	signal debug_pc_if : STD_LOGIC_VECTOR(31 downto 0);

	signal debug_asshole : STD_LOGIC_VECTOR(4 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: THE_MAIN_THING PORT MAP (
          clk => clk,
			 in1 => in1,
			 in2 => in2,
			 
          res1 => res1,
          res2 => res2,
			 
			 wb_stage_val => wb_stage_val,
			 wb_stage_dest => wb_stage_dest,
			 
			 exec_to_dm_alu => exec_to_dm_alu,
			 branch_and => branch_and,
			 debug_stall_if => debug_stall_if,
			 debug_pc_if => debug_pc_if,
			 
			 debug_asshole => debug_asshole
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
	in1 <= x"00000004";
	in2 <= x"00000004";
	
      -- hold reset state for 100 ns.
      wait for 100 ns;	

		

      wait for clk_period*10;

      -- insert stimulus here 

		wait for clk_period*10;
		
      wait;
   end process;

END;
